Advancements with multi-core processors and memory technologies (e.g., non-volatile memory (NVM) and solid state disks (SSDs) systems) enable information to be delivered among and within systems with increasing speed. However, these advances have not been optimized because, for example, storage input/output (I/O) throughput may be bottlenecked by interrupt processing.
Storage controllers help direct interrupts within systems and thus contribute to the interrupt processing bottleneck. Storage controller drivers direct interrupts by, for example, programming an I/O hub (IOH) or statically setting the controller's message signal interrupt (MSI) or message signal interrupt extended (MSI-X) control registers. Doing so enables the direction of interrupts on a per device basis. For example, the IOH may be set to a fixed-mode policy where interrupts are directed to a specific core. However, this may result in a single core becoming saturated by interrupt processing. Additionally, because the rest of the processing happens on another core, inter-processor interrupt (IPI) overhead is incurred.
To mitigate the saturation issue, the IOH can direct interrupts by spreading interrupts randomly or in a round-robin fashion to multiple processor cores. However, spreading interrupts can be problematic because servicing an I/O interrupt by a core different from where the corresponding request originated can cause contention and latency between the cores due to, for example, the mismatch of request/response processing contexts. The mismatch probability only increases with the number of processor cores.